1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus, imaging system, and photoelectric conversion apparatus manufacturing method.
2. Description of the Related Art
Photoelectric conversion apparatuses are roughly divided into a CCD (Charge Coupled Device) sensor and a CMOS (Complementary MOS) sensor. Early CMOS sensors generated large noise and were poorer in image quality than CCD sensors. However, today's advanced noise reduction technology allows CMOS sensors to attain image qualities equivalent to those of CCD sensors.
Japanese Patent Laid-Open No. 2004-153682 achieves high readout speeds by arranging two pairs of optical signal output lines (to be referred to as S output lines hereinafter) and noise signal output lines (to be referred to as N output lines hereinafter), and arranging two S/N readout circuits for amplifying and reading out difference signals from the two output lines. These output lines are arranged in order of the first S output line, first N output line, second N output line, and second S output line. This arrangement order makes the first S output line spaced apart from the second S and N output lines, reducing the coupling capacitance formed between the first S output line and the second S and N output lines. Similarly, the order makes the second S output line spaced apart from the first S and N output lines, decreasing the coupling capacitance formed between the second S output line and the first S and N output lines. The technique disclosed in Japanese Patent Laid-Open No. 2004-153682 can reduce crosstalk arising from capacitive coupling between two pairs of S output lines and N output lines.
Japanese Patent Laid-Open No. 11-330444 discloses a technique of forming a dummy pattern in a predetermined non-filter region except the array of color filters. The technique disclosed in Japanese Patent Laid-Open No. 11-330444 can assure the flatness of a planarization layer on the color filters to prevent defocusing and an image blur, and avoid degradation of the image quality caused by ambient scattered light. The technique can therefore improve the image quality of an image obtained by a CMOS sensor.
According to the technique disclosed in Japanese Patent Laid-Open No. 11-330444, a dummy pattern is formed of the same substance as a color filter to ensure the flatness of a planarization layer on the color filter. It is estimated that the dummy pattern is arranged in a large region except the pixel array region.
It is also estimated that, if the technique of Japanese Patent Laid-Open No. 11-330444 is applied to that of Japanese Patent Laid-Open No. 2004-153682, a dummy pattern is arranged even on two pairs of N output lines and S output lines. In this case, the dummy pattern raises the dielectric constant between output lines, compared to a case in which no dummy pattern for a color filter is formed on a plurality of output lines. The high dielectric constant between output lines owing to the dummy pattern increases the coupling capacitance between them. The coupling capacitance between the output lines may increase crosstalk.
As the distance between output lines is shortened at a high dielectric constant between them for reduction of the chip size, the coupling capacitance becomes larger in accordance with the shorter distance between them. This hinders shortening the distance between output lines by a predetermined amount or more, failing to downsize the chip.